ECE 375: Digital Design II

Class 11

Continuing VHDL Combinational Circuit

library ieee;
use ieee.std_logic_1164.all;

-- Describes the input, output, an name of a circuit
entity CKT1 is
port(
    A, B, C : in  std_logic;
    F       : out std_logic);
end CKT1;

-- Describes the behavior of the circuit
architecture CKT1_FUNC of CKT1 is
-- Define signals here
begin
    F <= (A and B) or C; -- Whatever logic you want to define
end CKT1_FUNC;

Level Triggered

A positive level triggered DFF would output D when the clock is high and will remember what the last D value was when the clock is low/rising/falling.