ECE 374: Computer Organization

Lab 2: Add/Sub Processor

Requirements

Objective: Upgrade the current MIPS processor to incorporate subtract instructions and encoding instructions into the processor for simulation.

Learning Outcomes:

• Understanding microprocessor organization and workings.
• Encoding instructions into machine language.
• Modification of existing VHDL code.

Theory (RCA to add_sub):

Currently, the microprocessor is equipped with a 4-bit Ripple Carry Adder (RCA) as shown below.

To incorporate addition and subtraction both, the RCA needs to be upgraded to an add_sub circuit, as shown below.

This circuit can perform both addition and subtraction. For addition, set Cin=0. For subtraction, set Cin=1.

This circuit was designed and simulated for Lab1.

Theory (encoding):

In MIPS, instructions are 32-bits long. R-type instructions are used for register-to-register operations like addition or subtraction. These instructions break down into the following 6 fields:

• Opcode: The operation code (e.g., add, subtract). It's always “000000” for R-type instructions.
• Rs: The first source register.
• Rt: The second source register.
• Rd: The destination register where the result is stored.
• Shamt: Shift amount (used for shift instructions, set to 00000 for add/sub).
• Funct: Specifies the exact operation (e.g., addition = 100000, subtraction = 100010).

Encoding Example: 𝐴𝑑𝑑 𝑅3,𝑅2,𝑅

This means we add the values in R2 and R4 and store the result in R3.

Here’s how this instruction looks in binary:

Machine Code: 00000_00010_00100_00011_00000_100000

Prelab:

Pre 1: Encode the instructions into machine code.

• Encode the following instructions into machine code.
  • r1 = r1 + r
  • r2 = r2 – r
  • r3 = r3 – r
  • r4 = r4 + r
  • r5 = r5 – r
• This will be used later.

Pre 2: Calculate the expected output.

• If the Register file is initiated as follows:
  • r0 = 0
  • r1 = 1
  • r2 = 2
  • r3 = 3
  • r4 = 4
  • r5 = 5
• Calculate the output for each instruction.

Lab Procedure:

Step 1: Open the project using Vivado.

• Extract the project files
• Launch Vivado and open the project or directly run the “add_isa.xpr” file from the project folder.

Step 2: Compile the project. To ensure that all files were downloaded correctly, run the project once.

• Run Synthesis
• Run Implementation
• Generate Bitstream

No need to run simulation, if there are any errors contact the instructor.

Step 3: Open the RCA’s VHDL file

• Select Project Manager (Left window in Flow Navigator window).
• Expand the Design Sources -> Expand add_isa -> open add_ins : ripple carry.

Step 4: Modify the RCA code to add_sub circuit.

You can refer/use the code from Lab 1 for this portion (Full Adder code is not required).

Do not change any naming such as “ripple_carry” or any of the input names.

• Declare a signal “Z” make this either a vector or declare four invividual bits (your choice).
• Write down the XOR equations after begin. (Refer to Lab 1 code)
• Change the “Y” inputs in port maps to “Z”.
• Save everything and compile the project (Run Synthesis and Run implementation).

Move to the next step if there are no errors.

Step 5: Open the Instruction Memory’s VHDL file

• From the Sources window select “instruction_memory” file.
• The following code should then open:

Step 6: Input the encoded instructions into the VHDL file

The constants im0, im1, im2, ...., im15 represents memory locations 0, 1, 2, ..., 15.

• Skip location 0 (im0).
• Type out the encoded instructions from prelab portion into the memory locations.

Use the format as shown in the sample instructions, doing so allows us to put “_” to create spacing between the different fields of the 32-bit instruction.

Step 7: Compile and run simulation

• Run Synthesis
• Run Implementation
• Run Simulation -> Run behavioral simulation
  • Goto Tools -> Run TCL Script
  • Select “Wave.tcl” file. (provided with the base code).
  • Right Click on waveform window and select “Full View”.
• Check if the simulated output matches with the expected output.

Each program counter value represents one instruction. i.e. PC=1 is instruction 1.

Note:

• You can get rid of the internal waves by selecting the wave and deleting it.
• You only need: clock, reset, current_pc and result, everything else is for debugging.

Move to the next step if the simulation matches with the expected output (Prelab 2).

Step 8: Program the FPGA board

• Generate Bitstream.
• Connect the Nexys Board to your system and turn it on
• Open Hardware Manager.
  • Click on Open target (Green bar on the top or bottom left)
  • Auto Connect
  • Hardware Manager should now change from “Unconnected” to “localhoast/Xilinx_tcf......”
• Program Device.

Step 9: Run the processor on the FPGA Board.

• Compare the FPGA outputs with the expected output values.
• Left LEDs are Result, Right LEDs are Program Counter
• Make SW0 = 1 and press the clock button.
  • This will reset the processor
• Make SW0 = 0
• Press Clock and compare result with expected value for Instruction 1
• Press Clock and compare result with expected value for Instruction 2
• Repeat the process for all the instructions.

Prelab

• r1 = r1 + r0 → add r1, r1, r0 → $000000_00001_00000_00001_00000_100000{2}$ → $0020_0820{16}$
• r2 = r2 – r0 → sub r2, r2, r0 → $000000_00010_00000_00010_00000_100010{2}$ → $0040_1022{16}$
• r3 = r3 – r0 → sub r3, r3, r0 → $000000_00011_00000_00011_00000_100010{2}$ → $0060_1822{16}$
• r4 = r4 + r0 → add r4, r4, r0 → $000000_00100_00000_00100_00000_100000{2}$ → $0080_4020{16}$
• r5 = r5 – r0 → sub r5, r5, r0 → $000000_00101_00000_00101_00000_100010{2}$ → $00A0_4822{16}$

Initial conditions:

• r0 = 0
• r1 = 1
• r2 = 2
• r3 = 3
• r4 = 4
• r5 = 5

Expected output:

• r0 = 0
• r1 = 1
• r2 = 2
• r3 = 3
• r4 = 4
• r5 = 5

VHDL Code