ECE 275: Digital Design I
Class 24-- N-bit PIPO Registry
library ieee;
use ieee.std_logic_1164.all;
entity pipo_reg is
generic (N : integer := 4); -- N is size 4 by default
port (CLK, RESET, LOAD : in std_logic;
DATA_IN : in std_logic_vector(N-1 downto 0);
DATA_OUT : out std_logic_vector(N-1 downto 0));
end entity;
architecture arch of pipo_reg is
begin
process (CLK)
begin
if CLK'event and CLK = '1' then
if RESET = '0' then
DATA_OUT <= (others => '0');
elsif LOAD = '1' then
DATA_OUT <= DATA_IN;
end if;
end if;
end process;
end architecture;
-- N-bit right shift register
-- He is making a 4 bit one but
-- I am making mine a generic one
-- so you can figure the rest
library ieee;
use ieee.std_logic_1164.all;
entity right_shift_reg is
generic (N : integer 4);
port (CLK, RESET, LOAD, DATA_IN : in std_logic;
DATA_OUT : out std_logic_vector(N-1 downto 0));
end entity;
architecture arch of right_shift_reg is
signal TEMP : std_logic_vector(N-1 downto 0);
begin
process (CLK);
begin
if CLK'event and CLK = '1' then
if RESET = '0' then
TEMP <= (others => '0');
elsif LOAD = '1' then
TEMP <= DATA_IN & TEMP(N-1 downto 1);
end if;
end if;
end process;
DATA_OUT <= TEMP;
end architecture;
-- N-bit PIPO Registry
library ieee;
use ieee.std_logic_1164.all;
entity pipo_reg is
generic (N : integer := 4); -- N is size 4 by default
port (CLK, RESET, LOAD : in std_logic;
DATA_IN : in std_logic_vector(N-1 downto 0);
DATA_OUT : out std_logic_vector(N-1 downto 0));
end entity;
architecture arch of pipo_reg is
begin
process (CLK)
begin
if CLK'event and CLK = '1' then
if RESET = '0' then
DATA_OUT <= (others => '0');
elsif LOAD = '1' then
DATA_OUT <= DATA_IN;
end if;
end if;
end process;
end architecture;
-- N-bit right shift register
-- He is making a 4 bit one but
-- I am making mine a generic one
-- so you can figure the rest
library ieee;
use ieee.std_logic_1164.all;
entity right_shift_reg is
generic (N : integer 4);
port (CLK, RESET, LOAD, DATA_IN : in std_logic;
DATA_OUT : out std_logic_vector(N-1 downto 0));
end entity;
architecture arch of right_shift_reg is
signal TEMP : std_logic_vector(N-1 downto 0);
begin
process (CLK);
begin
if CLK'event and CLK = '1' then
if RESET = '0' then
TEMP <= (others => '0');
elsif LOAD = '1' then
TEMP <= DATA_IN & TEMP(N-1 downto 1);
end if;
end if;
end process;
DATA_OUT <= TEMP;
end architecture;