ECE 275: Digital Design I

Class 7
library ieee;
use ieee.std_logic_1164.all;

entity circuit is
    port (A, B, C : in  std_logic;
          F, G    : out std_logic);
end;

architecture arch of circuit is
signal temp1, temp2 : std_logic;
begin
    temp1 <= not A;
    temp2 <= A and C;
    F <= temp1 and B;
    G <= not temp2;
end;

Binary Addition

0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 & carry 1

Example 1:

Base 10: 11 + 6 = 17 Base 2: 1011 + 110 = 10001 == 17

Example 2:

Base 2:

     1
     1
  11101
- 10011
--------
  01010

Base 10: 29 - 19 = 10

Example 2:

Base 2: 1111 * 1101

    1111
   *1101
--------
    1
  101111
  10000x
101111xx
 1111xxx
--------
11000011

Base 10: 15 * 13 = 195

Negative Numbers

3 ways to represent

  1. Sign and Magnitude
  2. 1's Complement
  3. 2's Complement
1's Complement

Just flip all the bits => -a = not a

N N
+0 0000 -0 1111
+1 0001 -1 1110
+2 0010 -2 1101
+3 0011 -3 1100
+4 0100 -4 1011
+5 0101 -5 1010
+6 0110 -6 1001
+7 0111 -7 1000

23 => 010111 -23 => 101000

Base 10: 5 - 5 = 0 Base 2:

0101
1010
----
1111 == -0 (Negative Zero?)